Double-diffusion metal oxide semiconductor (DMOS) transistors are a type of metal-oxide-semiconductor field effect transistors (MOSFETs) which are commonly used as power transistors. For example, DMOS power MOSFETs are widely used as power switching means in, for example, portable devices, automotive electrical systems and electronics, power supplies and power management systems, for controlling power flow from the power source to the load. One of the most fundamental requirements of a switching means is having very low power loss during power transferral between the power source and the load. To fulfil this requirement, it is highly desirable if the on-resistance of a DMOS power MOSFET can be made as low as possible.
A power MOSFET is usually formed by connecting a plurality of MOSFET cells in parallel for power applications such as high current switching applications. Parallel connection of the transistor cells enhances the current rating as well as reducing the on-resistance.
Trenched DMOS technology is common employed in the fabrication of DMOS power MOSFET devices for, for example, compact design. In the current trenched DMOS technology, a transistor is usually formed from square cells, hexagonal cells and strip cells. The square cell is commonly used to provide a compact design with a cell pitch of larger than 2.0 μm and with a trench width of about 1.0 μm. The strip cell design is commonly used when a higher cell density is required in order to reduce the on-state resistance. Examples of prior art trenched DMOS technology have been described in U.S. Pat. Nos. 5,341,011, 5,468,982, 5,474,943, 5,578,851, 5,877,528 and 5,904,525 which are incorporated herein by reference.
A trenched DMOS transistor cell is characterized by a trench which is formed in the substrate and which is lined with a thin oxide layer and then filled with a conductive polysilicon to form the transistor gate structure. In prior art trenched DMOS power MOSFET transistors, gate oxide breakdown is always a cause of device failure or premature damage which usually occurs during transistor switching. Hence, it is highly desirable if there can be provided trenched DMOS MOSFET devices with improved gate oxide breakdown performance as well as methods and processes for making same.
As the on-state resistance can be reduced by increasing the number of parallelly connected transistor cells and, to meet the requirements of a compact design, a high cell density is highly desirable. As cell density is largely determined by the cell pitch, it is therefore highly desirable if the cell pitch can be reduced or minimized. While the strip cell design is always used for high-density and compact transistor design, it is known that the minimum cell pitch is often limited by the lateral diffusion of source impurities into the device channel which will adversely affect the channel impurity concentration, thereby affecting the threshold voltage. In addition, it is known that the conventional strip cell design does not provide very good body contact which can degrade the on-state device performances such as current drive and latch-up immunity.
Furthermore, excessive polysilicon recesses in the trench, which results in a difference in height between the top surface of the polysilicon filling in the trench and the silicon substrate surface, may result in excessive threshold voltage variation due to undesirable penetration of impurities through the trench sidewalls into the device channel. This undesirable phenomenon is usually a result of conventional mass production processes and can hardly be avoided when conventional production processes are employed. Hence, it is highly desirable if undesirable penetration of impurities through the trench sidewall into the device channels can be prevented or, at least, alleviated for improved control of threshold voltage.